AMD has disclosed details for its Verano EPYC 9006 LP CPU architecture, a lineup designed specifically for Agentic AI deployments. The processors utilize the Zen 6 core architecture and are fabricated on the N2P process technology used in the EPYC 9006 Venice series. The chips will be available in configurations using either standard Zen 6 cores, which offer up to 12 cores per CCD, or Zen 6C cores, which provide up to 32 cores per CCD. This allows for maximum configurations of 72 cores with 144 threads or 192 cores with 384 threads.
The Verano processors feature significantly higher frequencies than previous generations, reaching up to 5.3 GHz on Zen 6 variants and 4.1 GHz on Zen 6C variants. This represents the fastest frequency ever recorded on EPYC CPUs. To support these speeds, the architecture includes an optimized CCD-to-IOD datapath with enhanced probe-response data and write-heavy traffic capabilities. The design also incorporates dual IODs, each containing 48 lanes of 64G SerDes and 8 lanes of 16G SerDes, providing a total of 96 PCIe Gen6 lanes.
A primary distinction between the Verano and Venice lineups is the memory subsystem. AMD has integrated LPDDR5X memory controllers into the design, with each IO die connected to two 6-channel LP5X controllers for a total of 24 channels. The platform supports speeds up to 8533 MT/s and utilizes field-replaceable SOCAMM2 modules. This new memory form factor is intended to provide high bandwidth and capacity while maintaining a compact footprint.
According to AMD, the use of LP5X SOCAMM memory on Verano platforms can offer up to 0.8 TB/s of bandwidth and up to 1.5 TB of capacity per socket. The company noted that this memory configuration lowers power draw by 30-40% compared to DDR5 RDIMM or MRDIMM at similar bandwidth levels. The processors are compatible with SB1 platforms, which enable up to 500W for compute, and are designed for use in AI-Host Nodes such as the Helion AI server.
