Qualcomm announced that its first-generation High Bandwidth Compute (HBC) silicon has been validated in its San Diego lab. The company reported that the chip successfully ran the complete memory read-write path and near-memory computations at production-representative dimensions using industry-standard automated test equipment. This hardware validation provides early evidence for a memory design specifically aimed at improving AI inference performance.
The HBC design addresses memory bandwidth constraints in large language model (LLM) inference by placing compute closer to memory to reduce data movement. Qualcomm's architecture stacks low-power LPDDR dies on top of an active AI accelerator base die using wafer-to-wafer bonding. This method reduces the distance data travels from millimeters to micrometers, resulting in an 18x increase in effective memory bandwidth over LPDDR5X and more than 5x the bandwidth per watt of projected HBM4 specifications.
While the company achieved significant efficiency gains, the results landed slightly below the 6x benchmark Qualcomm had previously projected. The company noted that these figures are estimates based on measured silicon results normalized to target operating conditions and compared with published competing product specifications. Qualcomm stated that final performance may vary depending on implementation, workload, and system configuration.
To mitigate defects in the stacked layers, the design incorporates redundancy and remapping to allow the hardware to work around faulty memory. The company has worked with foundry and assembly partners to qualify the wafer-to-wafer bonding process as part of a staged program spanning architecture, process development, and silicon validation.
Qualcomm's Dragonfly AI250 is expected to sample in the first half of 2027 and will be part of the Dragonfly Rack inference infrastructure. The hardware includes a full liquid-cooled rack featuring 38.6TB of memory and 7.4 petabytes per second of effective bandwidth. The company also plans to deploy its Oryon-based C1000 server CPU in 2027, followed by next-generation HBC in the Dragonfly AI300 in 2028.
