Tesla has disclosed a revamped roadmap for its AI hardware, introducing a new "Super Intelligence" branding for its accelerators and detailing significant performance leaps for future chips. The company plans to rename its inference accelerators with "SI" monikers, a move mirrored by Elon Musk's recent decision to rename SpaceXAI to SpaceXSI.
The roadmap includes the development of the Dojo D3 training accelerator, which will move away from the SRAM-centric, wafer-level integration used in the Dojo D1 and D2 generations. Instead, the D3 will utilize a multi-chiplet design incorporating 2.5D and 3D packaging technologies with stacked HBM to increase memory capacity. Tesla stated the D3 is being optimized for "space, training, and scaling," with specific optimizations intended for extraterrestrial deployments.
For its automotive inference hardware, Tesla expects its 6th Generation accelerator, the SI6, to deliver 80X the compute performance and 9X the memory of the current 4th Generation hardware. The SI6 is projected for release between 2029 and 2030. This follows the upcoming 5th Generation SI5, which Tesla expects will provide a 40X performance improvement over the current 4th Generation hardware through a combination of denser process technologies and silicon optimization.
The SI5 is scheduled to be manufactured using 3nm and 2nm-class process technologies at TSMC and Samsung Foundry, respectively. Unlike the conventional packaging used in the current 4th Generation processors, the SI5 will adopt a multi-chip module (MCM) design. Power consumption for the SI5 is expected to range from 250W to 800W depending on the specific application.
